[Libre-soc-dev] unauthorized SVP64 specification changes

[Luke Kenneth Casson Leighton]

On Monday, September 18, 2023, Jacob Lifshay <programmerjake at gmail.com>
wrote:

> maybe we should add a test that just creates a PowerDecoder2 by itself
> and just attempts to decode insns assembled by insndb? that way we can
> test decoding CR fields above 8 without needing to modify the whole
> simulator.

it's a really great idea that is much more complex than that:
PowerDecoder2 is augmented by SVP64DecodeExtra (something
like that), you'll have to dig into the source code of
TestIssuer to find the way the mappings actually work
and are stitched together.

basically the prefix goes into one HDL-class-instance
(SVP64RMDecode i think),
the suffix into PowerDecoder-with-Regfield-filters which
then gathers information to provide to PowerDecoder2,
*and* then the SVP64 RM-Decode "EXTRA" information, which
can only be decoded when the PowerDecoder tells you
the SVP64 Mode Type (NORMAL, CROPS, BRANCH, LDSTIMM, LDSTIDX),
can finally be *also* pushed into PowerDecoder2 and
*only then* can you get the full 7-bit register numbers out.

it is... seriously involved and extracting it into a single
"easy to test" unit would indeed be a quite important
(and quite big) task all on its own.

l.




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