[Libre-soc-dev] New AMD GPU BW Enhancing Shared L1 Cache

[Cole Poirier]

On Tuesday, October 6, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On 10/7/20, Cole Poirier <colepoirier at gmail.com> wrote:
>
> > Cool! Although I think this implementation deals with a NoC algorithm
> > too... Worth raising a bug report? Or just taking a look at it once we
> > start doing SMP work?
>
> yes because the organisation gives huge additional savings.  although
> it is designed for massive interconnect (1000 cores) rather than
> embedded level i.e. 4 to 8 cores
>

Ah makes sense. Though to clarify, are you replying yes to a) worth raising
a big report, or b) taking a look at it once we start doing SMP work?

I’m leaning towards b) but I can’t quite tell.

Cole