[Libre-soc-dev] daily kan-ban update 24nov2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Nov 25 14:44:46 GMT 2020


On Tue, Nov 24, 2020 at 7:14 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
>
> today: had a deeper look into the state machine of loadstore.vhdl
>        and thinking about ways to map this to the libre-soc architecture.
>        Also trying to understand how MultiCompUnit and multi-issue work.

MultiCompUnit is an augmentation of this simple diagram to make
operand1 and operand2 coverable by separate and independent RD/REQ
signals:
https://libre-soc.org/3d_gpu/comp_unit_req_rel.jpg

multi-issue in the scoreboard system creates "fake" transitive
dependencies, where the registers needed for the instruction in slot 1
"cascade" (become additional dependencies of) slots 2 3 and 4, those
in slot 2 cascade across 3 and 4 and those in slot 3 cascade across 4.

this incredibly simple scheme ensures that an ordering is preserved
between the instructions even though they are issued in the same
cycle.

l.



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