[Libre-soc-dev] soclayout/experiments10 doDesign.py

[Cole Poirier]

Running into the same error as a see on issue #30 but I can't figure
out how you solved it.

```
[ERROR] CParsVst() VHDL Parser - File:<./ls180.vst> Line:100531
        Port map assignment discrepency instance:0 vs. model:1
        Python stack trace:
        #0 in                  <module>() at
/home/colepoirier/alliance-check-toolkit/bin/doChip.py:321
```

Cole