[Libre-soc-dev] v3.1B prefix

[Alexandre Oliva]

On Dec  8, 2020, Alexandre Oliva <oliva at gnu.org> wrote:

> On Dec  7, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>> i did find it odd that there's no 16-bit imm instructions,

> Sorry, I failed to mention that they're not implemented yet.

Now they are.  I'm pretty sure the immediates for addi and addis are not
implemented according to the best use we could make of them, but the
shifts are as described in the specs.

I've also implemented conditinal register opcodes, system opcodes,
16-imm loads, stores, shifts, and compares; I put in code to parse
condition bit expressions and implemented bc[l] (16-imm) and bclr[l]
(10- and 16-bit).

Then I tested it all, reasonably lightly, and caught some errors:

- the new 16-imm insns were still being counted as 16+16-imm, fixed
their size computation

- tentative pairs of 10-bit nop + 16-imm, followed by 32-bit insn, were
silently backtracked to a single 32-bit insn; the backtracking is now
verbose and counted.  It doesn't affect size, but it makes more sense in
the stream and in the summary.

-- 
Alexandre Oliva, happy hacker  https://FSFLA.org/blogs/lxo/
   Free Software Activist         GNU Toolchain Engineer
        Vim, Vi, Voltei pro Emacs -- GNUlius Caesar