[Libre-soc-dev] Coloquinte legalizer failure

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Dec 5 14:07:57 GMT 2020


On 12/5/20, Staf Verhaegen <staf at fibraservi.eu> wrote:

>> however to do even a "dummy" P&R a dummy (phantom) cell that can be
>> placed is needed, isn't it?
>
> Yes, but you should be able to design RTL without needing to do P&R.

the whole idea is to help JP, who is overloaded, to eliminate many of
the early issues (ones that are related to placing *anything*,
regardless of layout, not ones specific to a specific PDK)

if he has to do everything this is significantly sub-optimal.

> As the SRAM block will likely be places manually best to discuss with
> JP how to proceed with this.

ok willdo


> So I assume you will go for usage of Instance in litex code ?
> In which tool do you want to simulate it ?

litex has verilator auto-building built-in.  it *should* just be
simulating sram....

ah you are thinking to have a special (verilog) model of that SRAM
cell and explicitly call it?  litex to code up a migen (not nmigen,
MIGEN) Instance?

and then to find the code where wishbone wrappere are made around
SRAM, and call it specially?

i know _how_ to do that (by cut/pasting a *lot* of litex code) and
migen code, all of which makes me nervous.

i would greatly prefer to use the standard sram Instance that verilog
expects, and to check that the simulated instance created by
*unmodified* verilator, unmodified litex, unmodified migen, has the
exact characteristics and size required.

when yosys is applied there and the cell is substituted.

does that sound reasonable?

l.



More information about the Libre-soc-dev mailing list