[Libre-soc-dev] daily kan-ban update 20aug2020

[Luke Kenneth Casson Leighton]

tasks:

* https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

am still going over the issue with FPGA litex Memory initialisation
not succeeding.  the current thinking is to create an alternative
wishbone "downconverter" that takes 64-bit and reduces to 32-bit.
this same code can also be used to do 128-bit (LoadStore) to 64-bit
thunking, meaning that the L0CacheBuffer does not have to.

l.