[Libre-soc-dev] libre-soc litex sim log

[Luke Kenneth Casson Leighton]

lkcl at fizzy:~/src/libresoc/soc/src/soc/litex/florent$ ./sim.py --cpu=libresoc

g++    veril.o sim_init.o verilated.o verilated_vcd_c.o Vsim__ALL.a
libdylib.o modules.o pads.o parse.o sim.o -lpthread -Wl,--no-as-needed
-ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent    -o Vsim
make[1]: Leaving directory
`/home/lkcl/src/libresoc/soc/src/soc/litex/florent/build/sim/gateware/obj_dir'
make: Leaving directory
`/home/lkcl/src/libresoc/soc/src/soc/litex/florent/build/sim/gateware'

[spdeeprom] loaded (addr = 0x0)
[clocker] loaded
[serial2tcp] loaded (0x56366fa64090)
[serial2console] loaded (0x56366fa64090)
[ethernet] loaded (0x56366fa64090)
[xgmii_ethernet] loaded (0x56366fa64090)

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Aug  6 2020 16:09:40
 BIOS CRC failed (expected 00004700, got a6d638b5)
 The system will continue, but expect problems.

 Migen git sha1: 731c192
 LiteX git sha1: 20ff2462

--=============== SoC ==================--
CPU:        @ 1MHz
BUS:        32-bit - 4GiB
CSR:       8-bit data
ROM:       64KiB
SRAM:      4KiB
MAIN-RAM:  262144KiB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--