[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=982

--- Comment #134 from Dmitry Selyutin <ghostmansd at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #133)
> dmitry just so you know (i will look at this tomorrow):
> 
>   11 * sc LEV
>   12 
>   13 Pseudo-code:
>   14 
>   15     SRR0 <-iea CIA + 4
>   16     SRR1[33:36] <- 0
>   17     SRR1[42:47] <- 0
>   18     SRR1[0:32]  <- MSR[0:32]
>   19     SRR1[37:41] <- MSR[37:41]
>   20     SRR1[48:63] <- MSR[48:63]
>   21     TRAP(0xC00)  <<<<--- this ACTUALLY calls ISACaller.TRAP(0xc00)
> 
> which you will find at... errr.... here:
> 
> 1318     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
> 1319         """TRAP> saves PC, MSR (and TODO SVSTATE), and updates MSR
> 1320 ...
>      ...
>      ....
> 1339         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
> 
> so yes, this is why you should find that SRR1[PIb.TRAP] has been set to 1
> because that's what ISACaller.TRAP() does.

Luke, I obviously found it (comment #128). I'd have expected this to be cleared
after return from interrupt, though; but that's just a logical expectation.

> but no bonus
> points given for doing so :)

I wrote the syscall generator, all the logic for emulation, several tests and
spent an awful lot of time debugging all parts of this. And for all this I got
1800 EUR. Thank you, I know there're no bonus points, there's no need to state
the obvious.

I'm hardcodimg the expected MSR in test. Not a single damn minute on this task
anymore.

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