[Libre-soc-bugs] [Bug 1044] SVP64 implementation of pow(x,y,z)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1044

--- Comment #56 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/sv/cr_ops/

## Format

SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:

|6 | 7 |19:20|21 | 22:23   |  description     |
|--|---|-----|---|---------|------------------|
|/ | / |0  0 |RG | dz  sz  | simple mode                      |
|/ | / |1  0 |RG | dz  sz  | scalar reduce mode (mapreduce) |
|zz|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode      |
|/ |SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |

nope, you're out of luck. not enough bits. that's annoying.
in *theory* it could be done... oh hang on! look, bit 6 is free!
it won't be perfect, ddffirst on CR-Field ops (3) would not be possible
but on CR-*bit* ops (5) such as cmpi not a problem.

okaay bugreport time, can you raise that jacob?
it'll need a TODO list involving
* spec
* powerdecoder
* insndb
* ISACaller unit tests
* binutils
* binutils unit tests

a lot of work nowadays.

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