[Libre-soc-bugs] [Bug 1178] FOSDEM 2024 Talk - Intro to PowerISA, SVP64, LibreSOC Extensions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1178

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Andrey Miroshnikov from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > (duplicate talks are frowned upon / not allowed at FOSDEM, they
> > have to be original and/or cover updates like tobias is doing.
> > that means you need to watch the 2021 and other videos in full
> > and ensure that the proposed material is NEW)
> Then I'd be happy to withdraw "Overview of LibreSOC", since as you've
> mentioned it's been covered in 2021.

brief reminder in another talk, first line of overview page and
say "go look at 2021 talk" is probably enough.
https://libre-soc.org/openpower/sv/overview/
thec2021 talk is even *on* that page.

> That leaves "Introduction to SimpleV and PowerISA+SVP64", I was hoping to go
> over some PowerISA assembler and SimpleV examples (HF, VF). 

yes VF is pretty new and people will totally get the significance of
saving on vector regsters.

the FFT complex number unit test is a damn good one (canonical).

a SIMD ISA which of course can only do horizontal has to waste
FOUR intermediate vector registers to be "performant", because
of the way you have to do real,imag = ra*ra-ri*ri, ra*ri-...
something like that, it is 4 multiplies (!) just for one piece
of data and in VF mode you can use SCALARS for all those temps
but source from the input vector *at the current loop offset*
and store likewise in the result vector at the same.

if the calculation is particularly complex you could end up
saving an absolutely massive amount of regs, even avoid memory spill
and keep to that critical LOAD-COMPUTE-STORE

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