[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

--- Comment #41 from Sadoon Albader <sadoon at albader.co> ---
Alright, finished up the first part of blocks.

I've decided not to create a test_svp64* file just yet, as that requires
rewriting the python implementation for poly1305 (class should inherit from
FHDLTestCase etc and that gave me many issues). I've decided to focus more on
the SVP64 part to get it working because once that works the rest can be done
easily.

A simple function to call ISACaller with the given lst and initial_regs:

def simulation_svp(lst,initial_regs):

    with Program(lst, bigendian=False) as program:
        sim = run_tst(program, initial_regs)
    return sim.gpr 

And we can then use the gpr in python, basically like inline asm.

The SVP64 implementation for the first part of blocks looks like this:

                'or 11, 9, 9', # move t0 to r11
                'rldicl 20, 9,  %d, 44' %(64-44), # equivelant to srdi
                'rldicr 21, 10, 20, %d' %(63-20), # equivelant to sldi
                'or 12, 20, 21', # move result to r12, 20&21 are temps
                'rldicl 13, 10, %d, 24' %(64-24),
                'or 13, 13, 30', # hibit or'ing, might be wrong but tests pass
                'setvl 0, 0, 3, 0, 1, 1',
                'sv.and *11, *11, *0',
                'sv.add *3, *3, *11',

Which is this in python:

            h0 += t0 & 0xfffffffffff
            h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff);
            h2 += (((t1 >> 24)             ) & 0x3ffffffffff) | hibit;

Then we can assert to check that the values are correct

            assert (h* == final_regs[*].value), "h* and h* simulation are
unequal!"


I've added a comment that the first part could use optimization but I think
I'll focus on the actual multiplication and addition first.

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