[Libre-soc-bugs] [Bug 1229] fosdem2024 llvm simple-v

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1229

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)
> some points:
> the register keyword won't be going away completely

whew

>
> register long a asm("r3");
> asm("addi r3, r3, 1" : "+r"(a));  // increments a

what i envision is that this:
   register long a[10] asm ("*r3")

literally traslates to
   setvl maxvl=10

and marks r3 as vector, such that sv.addi works as expected.
following on from that...

> for LLVM IR, we will be having standard existing vector IR translate to
> SimpleV ops in the backend, not something like having only SimpleV prefixed
> IR and never any vector ops or something like that.

... i then envisage an IR primitive that LITERALLY and precisely
without fail without exception represents the FULL and complete
capability of SV Prefixing. exactly precisely fully absolute
100% without fail absolute total and full representation of
the full absolute SV concept.

no vector instructions =>
no vector IR.

instead:

prefix isa =>
prefix hardware =>
prefix IR =>
prefix assembler.

we are ****NOT**** doing 1.5 million intrinsics. i am not
having it. no, caches are not ok. no, JIT-intrinsic-generation
is not ok.

if we have to invent a new IR syntax to support loop-prefixing
on top of (existing, small) scalar IR that is perfectly fine
with me.

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