[Libre-soc-bugs] [Bug 1229] New: fosdem2024 llvm simple-v

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1229

            Bug ID: 1229
           Summary: fosdem2024 llvm simple-v
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
               URL: https://pretalx.fosdem.org/fosdem-2024/me/submissions/
                    9GXYMY/
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Conferences
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
            Blocks: 1070
   NLnet milestone: ---

Your proposal: Simple-V not-vectorisation-but-looping: a Vector ISA without
Vector registers
Hi!

We have received your proposal "Simple-V not-vectorisation-but-looping: a
Vector ISA without Vector registers" to FOSDEM 2024. We will notify you once we
have had time to consider all proposals, but until then you can see and edit
your proposal at https://pretalx.fosdem.org/fosdem-2024/me/submissions/9GXYMY/.

Please do not hesitate to contact us if you have any questions!

The FOSDEM 2024 organisers

Full proposal content:

Proposal title: Simple-V not-vectorisation-but-looping: a Vector ISA without
Vector registers

Abstract: Simple-V Vectorisation is a RISC-paradigm Looping system implemented
at the Hardware ISA Level as a prefix similar to x86 REP, Z80 CPIR and LDIR (if
such were placed on a jet-propelled rocket sled of 5 years EU Grant /
NLnet-funded continuous development). There are NO Vector instructions: there
is only prefixing (and augmentation) of Scalar instructions, exactly as there
was (is) with 8086 REP. This "strict RISC-paradigm Prefixing" can expand an ISA
with 200 Scalar instructions into an extremely powerful "not-really-Vector"
Vector ISA with over one and a half million orthogonal RISC-uniform Vector
instructions.

With binutils support for Simple-V augentation of the Power ISA now stable, two
simulators for Power and RISC-V, it is time to consider compilers.

Our immediate thoughts are to leverage "int register[MAXVL] x;" where MAXVL is
statically defined by the programmer as needed. The hint that x is a
compile-time-fixed size on a per-function basis gives an extremely important
hint to the compiler that may be carried right the way through to the assembler
/ hardware level.

This talk therefore solicits feedback and discussion about adding both a
"Looping-Augmentation" IR token (to match directly to the Simple-V Prefix) as
well as the practicality of register arrays given that, annoyingly, the closed
C Standards body has deprecated the crucial register keyword.

Notes: The author has been subjected to 15 years of domestic verbal abuse and
as a result now has severe Post-Traumatic Stress Disorder. Combined with autism
and long-COVID health issues this makes it life-threateningly dangerous if
anyone is in any way aggressive, even indirectly, such as "normal"
confrontational questions or unintentionally hostile behaviour. The on-site RED
Cross will be informed as will senior FOSDEM Organisers.

Language: en

Software license(s): LGPLv3+

All presentations will be recorded and made available under Creative Commons
licences, CC-By-SA or CC-By. Please confirm that you agree to this.: Yes

I have read the FOSDEM Code of Conduct and agree to abide by it.: Yes


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=1070
[Bug 1070] Simple-V / Libre-SOC FOSDEM Conference Feb 03-04 2024
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