[Libre-soc-bugs] [Bug 864] implement parallel prefix reduction in simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=864

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > obviously it needs to do something different when one input is predicated
> > off and the other input is still on -- move (or something similar -- e.g.
> > integer subtract could be defined to assume predicated off inputs are
> > replaced with 0 so a - b with a predicated off would output -b).
> 
> unfortunately, changing the inputs to zeros would result in some instructions
> (multiply-prefix) outputting zero.

I meant that the input is Absent when that predicate bit is zero, not that the
input is replaced with zero. different instructions would handle absent inputs
different ways .. e.g. bitwise-and would treat an absent input as -1, division
could treat an absent input as 1.

imho this still follows the risc paradigm since the svp64 prefix could care
less which binary op it's reducing with, all it knows is it didn't supply some
of the inputs because those predicate bits were zeros.

-- 
You are receiving this mail because:
You are on the CC list for the bug.