[Libre-soc-bugs] [Bug 236] Atomics Standard writeup needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=236

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> these look to me like they're ok:
> https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html

that's the bare minimum for c++11 to operate correctly...it doesn't cover most
of the ops we want to be efficient.

also, c++11 has problems with atomic fences on power:
https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2017/p0668r1.html

imho we should introduce fences where needed that follow c++11 semantics.

imho we should also introduce fused atomic/fence ops, where the atomic
instruction is also a memory fence, like risc-v and armv8 and x86_64, this
would reduce the number of needed instructions for an acq_rel atomic add to 1,
rather than the 5-7 with a 4-instruction loop we currently have.

imho we should mirror risc-v's aq/rl bits:
aq rl:
0  0  relaxed
0  1  release
1  0  acquire
1  1  seq_cst

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