[Libre-soc-bugs] [Bug 865] implement vector bitmanip opcodes

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=865

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
I thought I had replied before, but apparently I forgot to click the submit
button.

(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to Jacob Lifshay from comment #3)
> > we'll also want shifting by 1 bit to cover finding up to and
> > including/excluding lowest set bit.
> 
> that's 6 mode bits
> 
> 
> > x ^ (x - 1) => set up to lowest set bit inclusive
> > (x ^ (x - 1)) >> 1 => set up to lowest set bit exclusive
> > 
> > we'll also want the option to bit-reverse both input and output so we can do
> > first set msb rather than first set lsb.
> 
> that's 8 mode bits.

it's actually 7, bit-reverse only happens on both or neither of the input and
output.

> 
> this needs 5 bits:
> 
> +def bmask(mode, RA, RB=None, zero=False):
> +    RT = RA if RB is not None and not zero else 0
> +    mask = RB if RB is not None else 0xffffffffffffffff
> +    a1 = RA if mode&1 else ~RA
> +    mode2 = (mode >> 1) & 0b11
> +    if mode2 == 0:
> +        a2 = -RA
> +    if mode2 == 1:
> +        a2 = RA-1
> +    if mode2 == 2:
> +        a2 = RA+1

this is redundant since RA + 1 == -(~RA)

> +    if mode2 == 3:
> +        a2 = ~(RA+1)

this is redundant since ~(RA + 1) = (~RA) - 1

removing both of those saves 1 more bit, making it 6 bits with all of my
proposed additions.

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