[Libre-soc-bugs] [Bug 858] SVP64 Primer Documentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=858

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> hmmm.. this image, which is how RISC-V works, i don't think
> helps us.

because it's too complex to explain. the Cray vector regfile is way simpler


     0  .....   63 elements

v0
v1
v2
..
v7

registers

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