[Libre-soc-bugs] [Bug 858] SVP64 Primer Documentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=858

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmmm.. this image, which is how RISC-V works, i don't think
helps us.  i totally get that it's based on an SRAM of a fixed
size: it just isn't how SV works.

https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=svp64-primer/img/vl_reg_n.jpg;hb=HEAD

SV is actually much more like how MMX works:

register r0:

    bytes    0  1  2  3  4  5  6  7
    64-bit  |<-------------------->|
    32-bit  |<--------->|<-------->|
    16-bit  |<--->|<--->|<--->|<-->|
    8-bit   |<->|    etc        |<>| 

register r1:

    bytes    0  1  2  3  4  5  6  7
    64-bit  |<-------------------->|
    32-bit  |<--------->|<-------->|
    16-bit  |<--->|<--->|<--->|<-->|
    8-bit   |<->|    etc        |<>| 

r2,3,4.......
.....r126

register r127:

    bytes    0  1  2  3  4  5  6  7
    64-bit  |<-------------------->|
    32-bit  |<--------->|<-------->|
    16-bit  |<--->|<--->|<--->|<-->|
    8-bit   |<->|    etc        |<>|

-- 
You are receiving this mail because:
You are on the CC list for the bug.