[Libre-soc-bugs] [Bug 858] SVP64 Primer Documentation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=858

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
important features and benefits to mention:

* The v3.1 Specification is not altered in any way.
* Predication, an often-requested feature, is added cleanly to the
  Power ISA (without modifying the v3.1 Power ISA)
* In-registers arbitrary-sized Matrix Multiply is achieved in three
  instructions (without adding v3.1 Power ISA instructions)
* Full DCT and FFT RADIX2 Triple-loops are achieved with dramatically
  reduced instruction count, and power consumption expected to greatly
  reduce. Normally found only in high-end VLIW DSPs (TI MSP, Qualcomm
  Hexagon)
* Fail-First Load/Store allows strncpy to be implemented in around 14
  instructions (Optimised VSX assembler is 240).
* Inner loop of MP3 implemented in under 100 instructions
  (gcc produces 450 for the same function)

All areas investigated so far consistently showed reductions in executable
size, which as outlined in {SIMD_HARM} has an indirect reduction in
power consumption due both to less I-Cache/TLB pressure and Issue remaining
idle.

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