[Libre-soc-bugs] [Bug 628] restore mistaken removal of OpenPOWER from wiki

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=628

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
./openpower/opcode_regs_deduped.mdwn:# OpenPOWER ISA register 'profile's
./openpower/sv.mdwn:# Simple-V Vectorisation for the OpenPOWER ISA
./conferences/ep2021.mdwn:* An OpenPOWER ISA simulator is written in python,
and is actually a PLY compiler based on the GardenSnake example
./conferences/ics2021.mdwn:The OpenPOWER ISA has a strong multi-decades pedig
ree in Supercomputing:
./nlnet_2021_crypto_router.mdwn:* Implemented the integer OpenPOWER ISA in a
libre-compatible Lattice FPGA (ECP5)
./nlnet_2021_crypto_router.mdwn:* Proprietary ISAs typically provide certain
aspects (GF8MULB - a byte-wise GF8 multiply that is only suitable for Rijndae
l) but do not provide general-purpose operations.  OpenPOWER provides hardcod
ed primitives for Rijndael MixColumns and SHA256 but not much else.
./3d_gpu.mdwn:  exploration started.  OpenPOWER ISA decoder started.  Two new
 people:
./docs.mdwn:| [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree)
 | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, IS
A spec compiler, co-simulation infrastructure |  [libresoc-openpower-isa](htt
ps://pypi.org/project/libresoc-openpower-isa/)  |
./resources.mdwn:# OpenPOWER ISA

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