[Libre-soc-bugs] [Bug 839] SVP64 / Extra-V / ZOLC whitepaper

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=839

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
looks great

new image, done just now:
https://ftp.libre-soc.org/20220614_122128.jpg

words:

Horizontal-First

setvl 8   (VL=8)
sv.addi 0.v, 0.v, 1
sv.muli 0.v, 0.v, 1

           Update Register Element order

Vertical-First
setvl 8   (VL=8)
sv.addi 0.v, 0.v, 1
sv.muli 0.v, 0.v, 1
svstep.
bc --->

and if you can space things out a bit, so the green arrows
between the Register updates (in red) are easy to follow?
use whatever style you think would be best, rather than
strictly follow what i did, ok?

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