[Libre-soc-bugs] [Bug 826] Trial run of ethmac (freecores) layout.

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=826

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)

> If that's supposed to hold a full ethernet packet, 

no. registers (and something called "BD", Buffer Descriptor, whatever
that is).

packets are transferred directly to/from FIFOs from/to memory
using a Wishbone Master interface.

in theory the SRAM could be made larger.

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