[Libre-soc-bugs] [Bug 909] Formal proof of nmutil/plru.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=909

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
actually, i want to modify PLRU's API somewhat so you can have a sram of PLRU
states and just one PLRU circuit rather than a bunch of dffs and PLRUs. the
sram would need 1 clocked write port and one combinatorial read port (unless
you want to wait an extra cycle), it would be external to PLRU.

so please don't close this one just yet

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