[Libre-soc-bugs] [Bug 838] sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=838

--- Comment #49 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Hooray, here's what my local binutils version produces:

  {
    .name = "sv.lwbrx",
    .desc = {
      .opcode = {
        .value = 0x7c00042c,
        .mask = 0xfc0007fe,
      },
      .in1 = SVP64_IN1_SEL_RA_OR_ZERO,
      .in2 = SVP64_IN2_SEL_RB,
      .in3 = SVP64_IN3_SEL_NONE,
      .out = SVP64_OUT_SEL_RT,
      .out2 = SVP64_OUT_SEL_NONE,
      .cr_in = SVP64_CR_IN_SEL_NONE,
      .cr_out = SVP64_CR_OUT_SEL_NONE,
      .sv_ptype = SVP64_PTYPE_P2,
      .sv_etype = SVP64_ETYPE_EXTRA2,
      .sv_in1 = SVP64_EXTRA_NONE,
      .sv_in2 = SVP64_EXTRA_IDX2,
      .sv_in3 = SVP64_EXTRA_NONE,
      .sv_out = SVP64_EXTRA_IDX0,
      .sv_out2 = SVP64_EXTRA_NONE,
      .sv_cr_in = SVP64_EXTRA_NONE,
      .sv_cr_out = SVP64_EXTRA_NONE,
    },
  },

Note that this already works with instruction database! I also was able to drop
some duplicated code. I hope that in a couple of days I'll be able to check the
Python code, fix the errors (including the one mentioned by Jacob) and
re-generate the C code. After this, I'll add the disassembler code which uses
the opcode.

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