[Libre-soc-bugs] [Bug 890] Static Timing Analysis of eth_mac

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=890

--- Comment #27 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
Been trying to get the basic inverter example to work. The example is located
here:
distrib/share/tutorials/hitas/inv

Chapter 5 Inverter example of hitas_tutorial.pdf goes over the db.tcl tcl file
used to generate the DTX, STM, and RCX databases (these are then used by the
"xtas" program).

To generate the databases, the user has to run the db.tcl script:
./db.tcl
(some other tests instead use 'run.tcl')

Here's the output:
Loading Spice netlist "./inv.spi"
Check level I (connectors)

               @@@@   @@@@    @    @@@@@@@@@@                    
                @@     @@    @@@   @   @@   @                    
                @@     @@     @   @    @@    @                   
                @@     @@              @@        @@@@     @@@@@@ 
                @@     @@  @@@@        @@       @@   @   @@    @ 
                @@@@@@@@@    @@        @@       @@   @@  @@@     
                @@     @@    @@        @@         @@@@@   @@@@   
                @@     @@    @@        @@       @@   @@     @@@@ 
                @@     @@    @@        @@      @@    @@  @    @@@
                @@     @@    @@        @@      @@   @@@  @@    @@
               @@@@   @@@@ @@@@@@    @@@@@@     @@@@  @@ @ @@@@@ 

                         AVERTEC Release v3.4p5 (64bit)

                  Copyright (c)1998-2022,  All Rights Reserved
                  E-mail: support at avertec.com
                  June 7th, 2010

LOADING FILE inv
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
DISASSEMBLING:
Check level II (nets)
Transistor netlist checking              00m00s  u:00m00.0  M:24296Kb
Extracting CMOS duals                    00m00s  u:00m00.0  M:24660Kb
Check level III (cones)
Extracting bleeders                      00m00s  u:00m00.0  M:24660Kb
Making gates                             00m00s  u:00m00.0  M:24660Kb
Latches detection                        00m00s  u:00m00.0  M:24660Kb
Making cells                             00m00s  u:00m00.0  M:24660Kb
External connector verification          00m00s  u:00m00.0  M:24660Kb
Checking the yagle figure                00m00s  u:00m00.0  M:24660Kb
------------------------------------------------------------
See file 'inv.rep' for more information
------------------------------------------------------------
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
CNS FILE inv.cns:
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
COMPUTING GATE DELAYS:
 00min 00s
hitas user   : 00'00.0''
      system : 00'00.0''
-----------------------------------
[Fatal Internal Error AVT-027]: Internal error, please contact Avertec support

The error occurs on line 19 of db.tcl, when calling 'hitas inv' tcl command.
This command pulls in the inv.spi spice file, and the error seems to be due to
declaration of the transistors used for the inverter:
MM02 y   a   gnd gnd tn L=0.18U W=1.15U AS=0.414P AD=0.414P PS=3.02U PD=3.02U
NF=20
MM03 y   a   vdd vdd tp L=0.18U W=2.23U AS=0.8028P AD=0.8028P PS=5.18U PD=5.18U
NF=20

Removing the parameters PS and PD (Source and Drain Perimeters, used to
calculate parasitic diode and capacitance) change the error to:
COMPUTING GATE DELAYS:
[Warning TRC-010]: The equivalent gate output load gives a negative capacitance
for signal y. 0 value is retained
[Error TRC-005]: Internal error #46 on net y.
** TOTAL ERRORS: 1
** TOTAL WARNINGS: 1

I'm not sure how to proceed, because I don't know what causes the Internal
error (AVT-027).

As I started writing this comment, I also ran the other tutorial tests.

addaccu, adder, blackbox, cpu2901, inv, lag, library, mipsr3000, ms,
multicycle, other_examples/hierarchy,mult,shift gives the same error as above
(AVT-027).

The other tutorials: clock_gating, counter, 
are stuck (or it takes more than 10min) :
FLATENNING THE FIGURE

h_macro has a test related to RC cache:
[Error MBK-006]: Can't flatten figure top because RC cache is active
** TOTAL ERRORS: 1
** TOTAL WARNINGS: 1

ssta/adder I'll start running now (it has monter-carlo statistical sim, so
takes a while).

I checked the log of the build.sh script, however I saw no warnings or errors.
It looks likes something is missing or not configured however.

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