[Libre-soc-bugs] [Bug 458] PartitionedSignal needs nmigen constructs "m.If", Switch etc

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=458

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
gaah.  another idea, which may be simpler to implement and is less disruptive
than temporary Signals *and* - maybe - has the potential to handle nested
Switch/case/If:

* override ast.Assign *as well* (PartitionedSignal.__Assign__,
  Value.__Assign__)
* at every SIMD Switch perform a full tree-walk of all AST searching
  for Assign statements
* append the test condition cases *onto the Assign*
* merge (AND) all test conditions together
* create a mini (leaf-node) Partitioned Switch with its
  own (private, leaf) for-loop, exactly as described
  in Comment #9

in other words, PartitionedSignal.__Assign__ becomes
a private (leaf node) Switch-for-loop-merged-with-Assign

the key strategic part is the merging (ANDing) together of all Switch
conditions that were created by dsl.py when parsing the user's HDL.

what is a huge relief is that this would *still* not require
a massive total replacement of dsl.py Module with a special
variant suitable for PartitionedSignal only.

-- 
You are receiving this mail because:
You are on the CC list for the bug.