[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to vklr at vkten.in from comment #19)
> def case_cmp(self):

> for cmp cr2, 1, 6, 7
> here gpr6 is 0x10 bigger than gpr7 0x5 so cr2 should be 0b010 instead of now
> evaluated 0b100

veera: we know that the instructions produce the right answer, they have
been tested against microwatt, etc etc.

therefore, we conclude that your current understanding of cmp
must be wrong.  i suspect you may have missed that for cmp, for
some bizarre reason, they swapped the args as compared to subf.

so to get the results *you* are expecting, it would have to be
cmp cr2, 1, 7, 6 not cmp cr2, 1, 6, 7 

basically this is very much a by-rote task (i apologise), except
when it comes to tests that have random input, in which case you
will need to actually compute the expected results "by hand" (python)

trust that the output is correct, ok? it's good you're reviewing
it though.

(In reply to klehman9 from comment #18)
> https://git.libre-soc.org/?p=openpower-isa.git;a=commit;
> h=0b7eb1cc2b6f1b820a54e668724f1e00967e85f3
> 
> cr regs were reversed

sigh, yes, Because Power ISA.  MSB0 numbering (VHDL "upto" not
"downto")

you would not believe how long it took to get things right and
get rid of bugs related to CR bit-ordering (MSB0). five frickin
months.

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