[Libre-soc-bugs] [Bug 698] ls180 ASIC test tasks

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=698

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #2)
> I think a block diagram of the SoC and a memory map of the IP blocks would
> also come handy during testing.

good point.  fortunately, very recently, the IBM India sponsored Educational
Course on OpenPOWER is running, the diagrams are here (and now in comment #0)
https://ftp.libre-soc.org/course_18oct2021/

diagrams 1 and 4 are the most useful.  memory map: basically autogenerated
by litex so needs to be "dug out" of the build process information, beyond
that, the one thing i made sure was that the UART was at the exact same
memory address as Microwatt.

oh, also, the boundary scan order.  manuel i must apologise, there was not
enough time to put it into "pinout sequential order", however hmm now that
i think about it, i can probably get the pinouts svg-generator program to
at least print out the offset and IOType.  or, update the program that
generated the pinouts page

https://libre-soc.org/180nm_Oct2020/ls180/

hmmm although i now realise, those are the die pinouts, not the *package*
pinouts, although there is a programmatic map for them in the autogeneration
of the SVG, i haven't had time to include that in the autogenerated
ls180.mdwn file

the offset and IOType is defined (python source code) here:
https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;h=1f3d424cbd7451c0434e0c71168f5aa0935af860;hb=9c233cbd457dd262e78d5b9c33b3aa4fb82febb7#l163

 163 class IOConn(Record):
 164     lengths = {
 165         IOType.In: 1,
 166         IOType.Out: 1,
 167         IOType.TriOut: 2,
 168         IOType.InTriOut: 3,
           }

yes, really, python to define HDL JTAG Boundary Scan Registers :)

i will dig up the sequence somehow, so that you know if you set JTAG
register X to 0b000100.... it sets a certain (expected) pad.

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