[Libre-soc-bugs] [Bug 736] New: SimdSignal's integration with nmigen needs to handle first args not being SimdSignals

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=736

            Bug ID: 736
           Summary: SimdSignal's integration with nmigen needs to handle
                    first args not being SimdSignals
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

e.g.:
s = SimdSignal(...)
Cat(Const(...), s)

Currently nmigen expects the first argument to always be a SimdSignal:
https://git.libre-soc.org/?p=nmigen.git;a=blob;f=nmigen/hdl/ast.py;h=39fb33f4d7bd36b33936c5e9f3f962aed7532150;hb=refs/heads/libresoc-partsig#l870

 870     # assume first item defines the "handling" for all others
 871     first, rest = args[0], args[1:]
 872     return first.__Cat__(*rest, src_loc_at=src_loc_at)

we should emulate Python's __add__ method selection logic, calling __Cat__ on
the farthest subclass in the input arguments.

See note in docs:
https://docs.python.org/3/reference/datamodel.html#object.__ror__

> If the right operand’s type is a subclass of the left operand’s type and that subclass provides a different implementation of the reflected method for the operation, this method will be called before the left operand’s non-reflected method. This behavior allows subclasses to override their ancestors’ operations.

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