[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #8 from vklr at vkten.in <vklr at vkten.in> ---
(In reply to klehman9 from comment #7)
> You would think, and call it a quirk, R0 is usually handled differently. 
> That's why in a lot of tests you see registers 3,2,1.
> 
> If you look at the psuedo code in PowerISA manual, you'll see
>   if RA = 0 then RT <-EXTS(SI || 16 0)
>     else RT <- (RA) + EXTS(SI || 16 0)
> 
> So basically when RA is 0 its value is ignored and the result is only
> shifted.

In here RA = GPR0 = 5

RT <- 5 + EXTS(1 || 16 0)

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