[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #3 from vklr at vkten.in <vklr at vkten.in> ---
Need help for understanding the construct and meaning.

def case_addis_nonzero_r0_regression(self):

lst = [f"addis 3, 0, 1"]

Here 3 means GPR3 register, 0 means GPR0 register and value of SI=1

initial_regs[0] = 5

here GPR0 is assigned value 5

e = ExpectedState(initial_regs, pc=4) ||| What does it do?

e.intregs[3] = 0x10000
is it here GPR3 is reassigned the value of 0x10000

self.add_case(Program(lst, bigendian), initial_regs, expected=e) ||| what this
does?

-- 
You are receiving this mail because:
You are on the CC list for the bug.