[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=731

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
confirmed: this is what happens:

/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/part/partsig.py:117:
DriverConflict: Signal '(sig sig)' is driven from multiple fragments: top,
top.pcat2; hierarchy will be flattened
  self.sig = Signal(*args, **kwargs)


lkcl at fizzy:~/src/libresoc/ieee754fpu/src$ git diff

--- a/src/ieee754/part/test/minitest_partsig.py
+++ b/src/ieee754/part/test/minitest_partsig.py
@@ -22,12 +22,19 @@ if __name__ == "__main__":
+    # RHS Cat
     m.d.comb += o.eq(Cat(a, b))
+    # LHS Cat
+    m.d.comb += Cat(a1, b1).eq(o)

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