[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #113 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #112)

> After thinking a bit, the actual issue is that element-widths are the thing
> arithmetic needs to happen on -- you can come up with whatever algorithm you
> like for deciding what full simd width to use, as long as the element widths
> take priority.

there are actually two separate and distinct cases.

1) the add6gs example you gave (which is the same as the rwlwinm example)

2) the times where the whole SIMD Signal is defined by the register file
   width (64 bit fixed width)

(2) will come *in* from the definition of the regspecs.

yes the priority is definitely (1) - to be honest we can probably get
away with not having (2) for now and see how it goes.

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