[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #3)
> Could you point me to example code with these blocks with 4-bit and 32-bit
> ports ?

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=8f881423e4aedfc38b4f35d78c842aec908cf990;hb=HEAD#l114

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/virtual_port.py;hb=HEAD

that's just one 32bit regfile for the standard Power ISA Condition Register
SVP64 needs *16* of these.

each 32bit CR has 8 CR Fields, 4 bits each.  these 4bit fields are accessed
by crand, cror etc. and the full 32bit by mcrf and mfcr.

with the 128 CR Fields being used for predication as well as Rc=1 targets
(vectorised) there will be a HELL of a lot of read and write ports onto
CRs.

to prevent delays we may need something like 4R3W or even 5R3W 32bit, with the
write-enable
being 8bit wide on each 4bit CR field

fortunately there would only be QTY 16 such 4R3W/5R3W 32bit regs.

it is perfectly fine to use one of those 32-bit ports to synthesise
the 4-bit ports via an adapter.  it is the opposite arrangement to
that virtual_port.py file but that's ok.

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