[Libre-soc-bugs] [Bug 724] Determine required memory compiler developments

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=724

--- Comment #2 from Staf Verhaegen <staf at fibraservi.eu> ---
Already comment from Luke in email:

'Yes.  i am trying to avoid more than one write port but if that's
possible (2W) it would be amazing and speed things up.

we do need 2W for the DMA buffers though.

if it is convenient i will be "stratifying" the regfiles so that they're
subdivided (interleaved), odd-even banks.

bank 1: r0 r2 r4 r6 r8 ...
bank 2: r1 r3 r5 r7 r9 ...

some of the very small regfiles (FAST, STATE, XER, CR) i would
actually recommend leaving them as DFFs.  the CR one is just
ridiculously complicated.  QTY 16of 32-bit regs comprising 4-bit
access *on top* of a (full) 32-bit access port.  multiple read-write
ports @ *both* 4-bit *and* 32-bit. plus the CR regfile is actually
unary-addressed (0b11111111 masks) for the LSBs, not
binary-addressed, but *binary* addressed for the MSBs
(selecting which of the 16).'

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