[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #58 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #56)
> (In reply to Luke Kenneth Casson Leighton from comment #53)
> 
> > yeah i'll do a (big) rename in the morning. SimdSignal?

go ahead and rename. I'll figure stuff out on monday.
> 
> realised it's best to wait for you respond before acting.

:) thx.

> i am still mulling over how and whether Par...^W SimdSignal
> can be adapted to support elwidths but also as a default
> option create full power-2 partitions and cover all
> permutations currently covered by PartitionedSignal.

oh, well all permutations currently covered by PartitionedSignal (at least
add/sub/logic-ops) are waay more than just the aligned, power-of-2 lanes.

I have an idea where there's a signal like SimdPartMode (which is: Simd split
into abstract "parts", which are combined to create lanes -- 1-bit signal per
part determines if a lane starts there), except each part_starts signal is an
enum:
class FpPartStartKind(Enum):
    NotAStart = 4 # only one with bit set, hopefully simplifying logic
    F16 = 1 # adjust to match elwid's definition
    BF16 = 2
    F32 = 3
    F64 = 0

this allows defining lanes like so (128-bit Simd so I can demo more
combinations):
part_starts = [
    FpPartStartKind.F16, # 1-part F16 lane in part 0
    FpPartStartKind.BF16, # 1-part BF16 lane in part 1
    FpPartStartKind.F32, # 2-part F32 lane in parts 2 and 3
    FpPartStartKind.NotAStart, # same lane as above
    FpPartStartKind.F64, # 4-part F64 lane in parts 4, 5, 6 and 7
    FpPartStartKind.NotAStart, # same lane as above
    FpPartStartKind.NotAStart, # same lane as above
    FpPartStartKind.NotAStart, # same lane as above
]

This may take a little more work to decode, and be more wires for part_starts,
but it covers everything that both the simd_signal code I wrote and the
layout() in comment #20 can do. it covers everything PartitionPoints can do,
too, though we'll probably still want to restrict lanes to be aligned, with
power-of-two part counts (since the part-width can be non-power-of-2, it can
still save space that way -- e.g. a lane can be 4 parts wide, since 4 is a
power-of-2, and parts can be 3-bits wide, allowing the lane to be 12-bits wide
since 12=4*3).

This layout can be converted to PartitionPoints, by just setting the partition
bit i * part_width for each part_starts[i] != NotAStart.

simd_signal.SimdPartMode.is_valid can be adapted to create a circuit used to
feed into an Assume to get only valid part_starts combinations (checks that
lanes are sized correctly, and are aligned correctly).

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