[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar, the Power Decoder works by reading CSV files, simply passing a list of
dictionaries to each PowerDecoder instance:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder.py;h=028de9b3b0f78cc488096ff74a2c57a458a75f77;hb=c9a4beb81e9c11a3ac70494dcf64850d8c3a6d1e#l518

however the svp64 "EXTRA" fields, as you can see in svp64.py, are organised
differently, keyed by the instruction (the comment field of v3.0B).

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;h=4955df75f7703fdab954fb814391ad4eab54326e;hb=c9a4beb81e9c11a3ac70494dcf64850d8c3a6d1e#l133

my feeling here is that get_csv should be replaced in power_decoder.py with a
function that "merges" the extra fields by looking up the instruction name and
simply dropping in the RM fields.

rather than modifying the CSV files which are already long.

what do you think?

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