[Libre-soc-bugs] [Bug 578] python-based svp64 "generator" class

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=578

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
field name "deducers" are in v3.0B section 1.7 page 16

they are:

* CRs:
  - 3 bit: BF and BFA
  - 5 bit: BA BB BC BI, BT
  - BO is... "odd", see section 2.4 "branch instructions"
  - FXM is a "mask" we ignore this one for now.
* GPRs: RA RB RC RS RT
* FPRs: FRA FRB FRC FRS FRT

confirm CRs with:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD#l479
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD#l543

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