[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #77 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #76)
> (In reply to Cesar Strauss from comment #75)
> > 2) I noticed that, for the CompUnit outputs, MultiCompUnit strips out the
> > *.ok ALU output fields by flattening the Data Record (*.data and *.ok) into
> > a Signal, truncating it.
> 
> 
> ah, right: if you find any of those... yyyees, strictly speaking this should
> not happen: there is supposed to be detection of the data/ok and to create a
> suitable Record, matching it.  i may have missed some of those and used
> Signal instead.

Sure.
Here, you see data_r is a Record:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compalu_multi.py;h=d7e32f28c556e76aff9be146ce280eba9745bb09;hb=HEAD#l268

A little below (line 281) it is appended to "drl".

Then, drl[i] is placed in dest[i]. which is a Signal:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compalu_multi.py;h=d7e32f28c556e76aff9be146ce280eba9745bb09;hb=HEAD#l356

The issue is actually mentioned in a comment, when dest[i] is created:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compalu_multi.py;h=d7e32f28c556e76aff9be146ce280eba9745bb09;hb=HEAD#l83

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