[Libre-soc-bugs] [Bug 508] decide package size and pin allocation for 180nm ASIC

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Sep 30 18:04:54 BST 2020


--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #7)

> > or can we get away with 32-32-32-32?
> The inner lead frame has 32 IO connections on each side so the latter.

excellent.  no redesign work of ioring.py needed or the pinmux ls180.py

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