[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Tue Sep 29 17:14:55 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=485
--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #7)
> (In reply to Luke Kenneth Casson Leighton from comment #5)
> > 1119 # -- Process cache invalidations
> > 1120 # if inval_in = '1' then
> > 1121 # for i in index_t loop
> > 1122 # cache_valids(i) <= (others => '0');
> > 1123 # end loop;
> > 1124 # r.store_valid <= '0';
> > 1125 # end if;
> > 1126 # Process cache invalidations
> > 1127 with m.If(inval_in):
> > 1128 for i in range(NUM_LINES):
> > 1129 sync += cache_valid_bits[i].eq(~1)
> >
> > line 1122 says "set to zero". why set to ~1?
>
> I thought vhdl '(others => '0')' nmigen equivalent was ~1,
no, it's "set all other bits to zero". it says "0".
you meant (are confusing this with) "others => '1'
that asks for "all other bits to be set to 1."
and the way to do that is to set eq(-1) which is the same as eq(~0)
> doing just eq(0)
> you said, only sets the first bit to 0,
no i did not. i said, "all nonspecified bits are set to zero i.e eq(0) is
zero-extended"
> where '(others => '0')' sets all
> bits to zero.
yes.
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