[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #21)

> FORTNUATELY, for SDRAM, the concept of alternative PHYs is an
> established practice, so i "only" have to create a replacement
> that munges the names of dq into triple-functions dq_i, dq_o, dq_en

done.

commit 28638852cc74861c4fb5095aa1e712f26b3f364a (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Sep 23 22:44:56 2020 +0100

    change litex sdram pinouts to ASIC type

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