[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Sep 22 13:00:30 BST 2020


--- Comment #27 from Cesar Strauss <cestrauss at gmail.com> ---
Some updates:

1) The design now works under both pysim and cxxsim.

2) To gain experience, ended-up writing a formal proof for it, with coverage,
bounded model check, and induction:



Note that this proof relies on the FSM nature of the Shifter (at most one
operation in flight), and will likely not work on a pipelined design.

Next steps:

1) I think the FSM can have a shortcut from DONE directly to SHIFT (bypassing
IDLE) when the output data is accepted, and there is already an input waiting.
It should avoid wasting one clock period, improving throughput.

2) Maybe, add a logarithmic pipelined shifter, for comparison.

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