[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
next bit is to hook up chips4makers jtag which has a wishbone bus master on it,
and investigate ways to test it.

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