[Libre-soc-bugs] [Bug 488] Build test serdes on 180nm test chip for oct2020

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Sep 10 21:24:49 BST 2020


--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Staf Verhaegen from comment #3)
> Prof. Dimitri Galayko @ LIP6 is already working on a PLL for the tape-out
> including a VCO.

IIRC that particular VCO design doesn't have 4 output phases and isn't designed
to run at 10GHz since our processor core won't ever be running that fast.

What I wanted to do is more of building and testing the digital logic for the
serdes rather than focusing on the VCO -- I figured that since we're taping out
a test chip anyway, if we have time, we might as well put an experimental
serdes design on there to see if it might work and what speeds it works at.
That could influence our decision for if we should include a similar serdes
running at 50Gbaud for OMI on 40nm/28nm with a VCO designed by someone with
more experience.

> I don't see how you guys could do an analog design for the October tape-out
> as you don't have access to the PDK.

That's true, however, if it doesn't take much work to do the digital side of
the serdes, the only non-standard cells needed would be the capacitor for
storing the control voltage, a much smaller capacitor for the charge pump for
adjusting the control voltage, and the variable delay circuit. I'd guess that
the capacitors aren't very much work, and the delay circuit might take a day or
two for you to draw.

> Also the paper is just a simulation
> excercise which has not been verified in silicon.

True, if it doesn't work it most likely won't affect the test chip much, all
you do is tell the cpu not to access that particular peripheral and use a
transmission gate to short the control voltage capacitor to ground, causing the
experimental VCO to stop.

If it does work, it would be great evidence that the 50Gbaud serdes would
probably work on 40nm/28nm.

> I would also think there is enough to do on the digital side for the Power
> core + GPU extension for the October tape-out.

The october tape-out probably won't actually have any GPU extensions since
those aren't even out of the ISA design stage yet.

The Power core is mostly working on a FPGA, so the stuff that's left for the
oct tapeout is adding a MMU and more peripherals IIRC.

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