[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Sep 7 13:22:09 BST 2020


--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
                comb += wr_addr.eq(r1.store_row)
                comb += wr_sel.eq(~0) # all 1s

#                 if r1.state = RELOAD_WAIT_ACK and
#                 wishbone_in.ack = '1' and replace_way = i then
            with m.If((r1.state == State.RELOAD_WAIT_ACK)
                      & wishbone_in.ack & (relpace_way == i)):

you need to make sure that any comparisons are in brackets when included
with "&" or "|" bit-wise operators.

the reason is because unlike "and" and "or", "&/|" are HIGHER precedence
than comparisons.

in python you would normally do "if x & mask == 0b110" and that would of
course be taken to mean "bit-wise AND x together THEN compare against 0b110".

so it is critically important to do "if (x & mask) == 0b110" and it is
ESPECIALLY important to do "value & (something == somethingelse)" otherwise
it is interpreted as "(value & something) == somethingelse"

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