[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #132 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #130)
> alexander: ok, i added the FSM to the Appendix, along with a clear and
> unequivocal separation between Phase 1 and Phase 2, explicitly stating
> precisely and clearly what their roles and responsibilities are
> 
> https://libre-soc.org/openpower/sv/16_bit_compressed/
> 
> again to reiterate, i cannot emphasise enough how critically important it is
> that you understand and accept the distinction between these two phases.
> 
> note in particular: ONLY phase 2 looks further at N/M to ascertain if the 16
> bit instruction is the 16bit.immediate variant.
> 
> this is *NOT* relevant - at all - to Phase 1 because Phase 1's sole
> exclusive task, to the exclusion of all else, is to determine length+mode,
> and to communicate that to Phase 2, through a pipeline, in a fowarding-only
> fashion.

Note that the efficient decoding example actually splits it into 3 phases (only
first 2 included in linked example):
https://libre-soc.org/openpower/sv/16_bit_compressed/decoding/
phase 1:
determine instruction sizes/next encoding modes for all possible current
encoding modes at each 16-bit boundary.
phase 2:
do an efficient parallel prefix-sum algorithm O(log N) to determine the
encoding mode, starting offset, and instruction size of all instructions in the
decode window.
phase 3:
pick the first few instructions and decode them fully.

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