[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #82 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #81)

> One other confusing difference is that the PowerISA spec uses inclusive
> ranges, yet nmigen/Python/Rust/C++/... all use half-open ranges by default:
> low <= element < high

and if you want people to witness a mushroom cloud coming out the top of your
head: conversion of microwatt's vhdl code has inclusive hi downto lo but
vitconcatenation is expressed in the inverse order to python but numerical
constants are not.

https://www.youtube.com/watch?v=UIKGV2cTgqA

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