[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
[master 7400c18] start connecting up Pi2LSUI

okok i was bored, i started on it :)

looking at lsmem.py, it occurs to me that simply hooking up
BareMemoryLoadStoreUnit / CacheLoadStoreUnit to harry ho's
sram.py the exact same unit test could be used.

and that that could be done through that reconfigureable
class in bug #403.

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